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Single-Cycle Read and Write
Figure 6-1 to Figure 6-3 on page 54 show basic single-cycle read and write accesses to the backend. The core will pulse
DP_START active and indicate whether it is a read or write cycle and which BAR is being accessed. BAR_SELECT
and RD_CYC/WR_CYC will become valid on the same clock cycle where DP_START is asserted and will remain
active until DP_DONE is asserted. They are deasserted on the clock cycle after DP_DONE. Although the PCI
interface requests only a single data word read, the core may read more than one word from the backend interface.
For read cycles, the core indicates that it is ready to read data by asserting RD_STB_OUT. The backend logic indicates
that it has data available by asserting RD_STB_IN. When both of these signals are active, the core will read data from
the backend. If RD_SYNC = 0, data is sampled on the clock edge during which the strobes are active ( Figure 6-1 ).
When RD_SYNC = 1, data is sampled on the following clock edge ( Figure 6-2 on page 53 ).
The PCI specification states that the maximum delay from FRAMEN assertion to the first data word transferred on the
PCI bus is 16 clock cycles. The core takes two clock cycles from the time FRAMEN is asserted to assert DP_START.
RD_STB_OUT is asserted one clock cycle later, and then an additional two clock cycles are required for the data to pass
back through the core.
The backend must assert RD_STB_IN within 11 clock cycles. If the backend does not assert RD_STB_IN within this
time, the core will automatically terminate the PCI transfer with a Target retry. When RD_SYNC = 1, an additional
cycle of delay is added at the backend interface, reducing the initial backend latency to 10 clock cycles.
Once a data burst has started, data must be transferred every eight clock cycles. If the backend fails to provide data at this
rate, the core will terminate the PCI cycle with a disconnect without data to maintain PCI compliance.
When the SX-A or RTSX-S families are used, the core inserts an additional clock cycle of latency internally. Thus, in
this case, the backend maximum initial latency is reduced by one clock cycle. This is summarized in Table 6-2 on
cycle
0
1
2
3
4
5
6
clk
framen
cben[3:0]
ad[31:0]
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
6
ADDR
0
0
0
mem_add[15:0]
mem_data_in[31:0]
0000
0
0004
1
0008
2
rd_sync
Figure 6-1 · Backend Read Cycle (RD_SYNC = 0)
52
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